A lateral diffused metal oxide semiconductor transistor (i.e., LDMOS transistor) is suitably used for a semiconductor device such as an electronic control unit (i.e., ECU) for controlling an automotive vehicle and an ECU for controlling electronic equipment. Specifically, the LDMOS transistor works as a power device (i.e., a power integrated circuit). An electrostatic discharge (i.e., ESD) surge is sometimes applied to the LDMOS transistor. For example, the LDMOS transistor used for the vehicle is required to have a large withstand capacity against the ESD surge (i.e., a large ESD surge withstand capacity). Specifically, the withstand capacity of the LDMOS transistor is, for example, about 15 kV in a case where the ESD surge has an impedance of 150 Ω and 150 pF. When the ESD surge is applied to the transistor, a transient current flows between terminals of the LDMOS transistor. The transient current changes with time. The maximum transient current, i.e., a surge current, is, for example, about 200 Ampere in a case where the transistor is used for an automotive vehicle. When the surge current is applied to the LDMOS transistor, the current concentrates into a local portion of the LDMOS transistor in a case where a device area of the LDMOS transistor is comparatively small. This concentration of the current is caused by a snap back effect. The snap back effect is such that a negative resistance is generated in a current-voltage characteristic of the LDMOS transistor. Therefore, the local portion of the LDMOS transistor may be melted thermally so that the LDMOS does not work (i.e., the LDMOS transistor fails).
In a conventional LDMOS transistor, the device area is small. Therefore, it is difficult to protect the LDMOS transistor from locally melting down. Therefore, a protection device as an external circuit is added to the LDMOS transistor so that a required withstand capacity against the ESD surge is obtained. However, when the protection device as the external circuit is added, a cost of the semiconductor device becomes higher. Further, dimensions of the semiconductor device become larger.
In a case where the device does not have the protection device, the device area of the LDMOS transistor is equal to or smaller than 1 mm2, which satisfies the required withstand capacity economically. Since the maximum ESD surge current is 200 Ampere (i.e., 200 A), the maximum surge current density per unit area Imax is equal to or larger than 200 Ampere per square millimeters (i.e., 200 A/mm2). A LDMOS transistor having the withstand capacity against the maximum surge current density Imax of 200 A/mm2 is disclosed in Japanese Patent Application Publication No. 2001-352070 (i.e., U.S. Pat. No. 6,465,839 and No. 6,573,144). One cell of the LDMOS transistor 300 is shown in FIG. 13. In the actual LDMOS transistor 300, the one cell shown in FIG. 13 and another cell, which is provided by reversing the one cell horizontally, are alternately repeated. That is, the one cell and the other cell are symmetrically and alternately disposed in the LDMOS transistor 300.
The LDMOS transistor 300 is formed on a SOI (i.e., silicon on insulator) substrate having a P conductivity type silicon substrate 302, an insulation layer 303 and an N conductivity type layer 301. In the LDMOS transistor 300, an N conductivity type region 306 surrounds an N+ conductivity type drain region 305. The impurity concentration of the N conductivity type region 306 is higher than that of the N conductivity type layer 301. Further, the impurity concentration of the N conductivity type region 306 becomes higher as it approaches the N+ conductivity type drain region 305. A P+ conductivity type contact region 309 is disposed adjacent to an N+ conductivity type source region 308. The P+ conductivity type contact region 309 is disposed under the N+ conductivity type source region 308. Further, a P conductivity type base region 307 as a channel is disposed under the P+ conductivity type contact region 309 and under the N+ conductivity type source region 308. A LOCOS (i.e., local oxidation of silicon) region 304 is disposed between the P conductivity type base region 307 and the N conductivity type region 306. A gate insulation film 310 is disposed on the N conductivity type layer 301. A gate electrode 311 is disposed on the N conductivity type layer 301 through the gate insulation film 310. An interlayer insulation film 312 covers the gate electrode 311 and the LOCOS region 304. A source electrode 313 is disposed on one side of the interlayer insulation film 312, and a drain electrode 314 is disposed on the other side of the interlayer insulation film 312.
In the LDMOS transistor 300, the impurity concentration of the N conductivity type region 306 becomes higher as it approaches the N+ conductivity type drain region 305, so that a generation current at a break point in current-voltage characteristics becomes large. Further, the P+ conductivity type contact region 309 is arranged in a predetermined position shown in FIG. 13 so that a parasitic transistor composed of the N+ conductivity type source region 308, the P conductivity type base region 307 and the N conductivity type layer 301 is prevented from turning on. Therefore, the ESD surge withstand capacity of the LDMOS transistor 300 is improved.
In the LDMOS transistor 300, when the impurity concentration of the N conductivity type region 306 is in a range between 5×1016/cm3 and 2×1017/cm3, the ESD surge withstand capacity of the LDMOS transistor 300 becomes maximum. However, when the dimensions of the N conductivity type region 306 are certain values, the ESD surge withstand capacity is reduced. Therefore, the LDMOS transistor 300 may not satisfy the required withstand capacity.